The position value is transmitted synchronously to the clock signal of the control system, starting with the most significant bit (MSB).
When non-operational, the clock as well as the data line is high. As soon as the clock signal of a clock sequence changes for the first time from low (L) to high (H), the bit-parallel data on the parallel-serial-converter will be stored via an internal SLoad-Signal in the input latch of the shift register. This ensures that the data cannot change during the transmission of a position value. With the following rising edge transition of the clock signal, the transmission begins with the most significant bit (MSB).
With each following rising edge transition of the clock signal, the next lower significant bit is set on the output of the data line. After the least significant bit is shifted out, the last rising edge transition of the clock signal switches the data line to low (transmission end).
After the last falling edge of the clock signal, a retriggerable mono-flop determines with its internal delay time tm, how long it will take until the rotary encoder or another encoder can be selected for the next transmission. With this, the minimal admissible break time between two successive clock sequences is determined.